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data sheet low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 853S111AI 853S111AI rev a 6/30/15 1 ?2015 integrated device technology, inc. general description the 853S111AI is a low skew, high performance 1-to-10 differential-to-2.5v/3.3v l vpecl/ecl fanout buffer. the 853S111AI is characterized to operat e from either a 2.5v or a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the 853S111AI ideal for those clock distribution applications demanding well defined performance and repeatability. features ten differential 2.5v, 3.3v lvpecl/ecl outputs two selectable differential input pairs pclkx, npclkx pairs can accept the following differential input levels: lvpecl, lvds, sstl, cml maximum output frequency: 2.5ghz translates any single-ended input signal to 3.3v lvpecl levels with resistor bias on npclk input output skew: 55ps (maximum) part-to-part skew: 250ps (maximum) propagation delay: 780ps (maximum) additive phase jitter, rms: 0.07ps (typical) lvpecl mode operating voltage supply range: v cc = 2.375v to 3.465v, v ee = 0v ecl mode operating voltage supply range: v cc = 0v, v ee = -3.465v to -2.375v -40c to 85c ambient operating temperature available lead-free (rohs 6) package 853S111AI 32-lead lqfp 7mm x 7mm x 1.4 mm package body y package top view pin assignment block diagram q0nq0 q1 nq1 clk_sel pclk0 npclk0 0 1 pulldown pullup/pulldown pulldown v bb q2nq2 nq3 nq3 pclk1 npclk1 pulldown pullup/pulldown q4nq4 q5nq5 q6 nq6 q7nq7 nq8 nq8 q9nq9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 2526 27 28 2930 31 32 1615 14 13 1211 10 9 v cco nq2 q2 nq1 q1 nq0 q0 v cco v cco q7 nq7 q8 nq8q9 nq9 v cco v cc clk_sel pclk0 npclk0 v bb pclk1 npclk1 v ee nq3 q4 nq4q5 nq5 q6 nq6 q3
rev a 6/30/15 2 low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 853S111AI data sheet table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1v cc power positive supply pin. 2 clk_sel input pulldown clock select input. when high, select s pclk1, npclk1 inputs. when low, selects pclk0, npclk0 inputs. lvpecl in terface levels. also accepts standard lvcmos/lvttl input levels. 3 pclk0 input pulldown non-inverting differential lvpecl clock input. 4 npclk0 input pullup/ pulldown inverting differential lvpecl clock input. v cc /2 default when left floating. 5v bb output bias voltage to be connec ted for single-e nded lvpecl input. 6 pclk1 input pulldown non-inverting differential lvpecl clock input. 7 npclk1 input pullup/ pulldown inverting differential lvpecl clock input. v cc /2 default when left floating. 8v ee power negative supply pin. 9, 16, 25, 32 v cco power output supply pins. 10, 11 nq9, q9 output differential output pair. lvpecl/ecl interface levels. 12, 13 nq8, q8 output differential output pair. lvpecl/ecl interface levels. 14, 15 nq7, q7 output differential output pair. lvpecl/ecl interface levels. 17, 18 nq6, q6 output differential output pair. lvpecl/ecl interface levels. 19, 20 nq5, q5 output differential output pair. lvpecl/ecl interface levels. 21, 22 nq4, q4 output differential output pair. lvpecl/ecl interface levels. 23, 24 nq3, q3 output differential output pair. lvpecl/ecl interface levels. 26, 27 nq2, q2 output differential output pair. lvpecl/ecl interface levels. 28, 29 nq1, q1 output differential output pair. lvpecl/ecl interface levels. 30, 31 nq0, q0 output differential output pair. lvpecl/ecl interface levels. symbol parameter test conditions minimum typical maximum units r pulldown input pulldown resistor 75 k ? r vcc/2 pullup/pulldown resistors 50 k ?
low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 3 rev a 6/30/15 853S111AI data sheet function tables table 3a. clock input function table note 1: please refer to the applications information, ?w iring the differential input to accept single ended levels?. table 3b. control input function table inputs outputs input to output mode polarity pclk0 or pclk1 npclk0 or npclk1 q0:q9 nq0:nq9 0 1 low high differential to differential non-inverting 1 0 high low differential to differential non-inverting 0 biased; note 1 low high single-ended to differential non-inverting 1 biased; note 1 high low single-ended to differential non-inverting biased; note 1 0 high low single-ended to differential inverting biased; note 1 1 low high single-ended to differential inverting inputs clk_sel selected source 0 pclk0, npclk0 1 pclk1, npclk1
rev a 6/30/15 4 low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 853S111AI data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = v cco = 2.375v to 3.465v; v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 4.6v (lvpecl mode, v ee = 0v) negative supply voltage, v ee -4.6v (ecl mode, v cc = 0v) inputs, v i (lvpecl mode) -0.5v to v cc + 0.5v inputs, v i (ecl mode) 0.5v to v ee ? 0.5v outputs, i o continuos current surge current 50ma100ma v bb sink//source, i bb 0.5ma operating temperature range, t a -40 ? c to +85 ? c package thermal impedance, ? ja 80.9 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v cc positive supply voltage 2.375 3.3 3.465 v v cco output supply voltage 2.375 3.3 3.465 v i ee power supply current 74 ma
low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 5 rev a 6/30/15 853S111AI data sheet table 4b. lvpecl dc characteristics, v cc = v cco = 3.3v; v ee = 0v, t a = -40c to 85c note: input and output par ameters vary 1:1 with v cc . v ee can vary +0.925v to -0.5v. note 1: outputs terminated with 50 ? to v cco ? 2v. note 2: single-ended input operation is limited. v cc ? 3v in lvpecl mode. note 3: common mode voltage is defined as v ih . . table 4c. lvpecl dc characteristics, v cc = v cco = 2.5v; v ee = 0v, t a = -40c to 85c note: input and output par ameters vary 1:1 with v cc . v ee can vary +0.925v to -0.5v. note 1: outputs terminated with 50 ? to v cco ? 2v. note 2: common mode voltage is defined as v ih .. symbol parameter -40c 25c 85c units min typ max min typ max min typ max v oh output high voltage; note 1 2.27 2.36 2.45 2.16 2.33 2.45 2.06 2.32 2.45 v v ol output low voltage; note 1 1.44 1 .58 1.71 1.41 1.55 1.71 1.33 1.54 1.71 v v ih input high voltage (single-ended) 2.075 2.36 2.075 2.36 2.075 2.36 v v il input low voltage (single-ended) 1.43 1.765 1.43 1.765 1.43 1.765 v v bb output voltage reference; note 2 1.86 1.98 1.86 1.98 1.86 1.98 v v pp peak-to-peak input voltage 150 800 1200 150 800 1200 150 800 1200 v v cmr input high voltage common mode range; note 3 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current pclk0, pclk1 npclk0, npclk1 200 200 200 a i il input low current pclk0, pclk1 -10 -10 -10 a npclk0, npclk1 -200 -200 -200 a symbol parameter -40c 25c 85c units min typ max min typ max min typ max v oh output high voltage; note 1 1.47 1.56 1.65 1.36 1.53 1.65 1.26 1.52 1.65 v v ol output low voltage; note 1 0.64 0 .78 0.91 0.61 0.75 0.91 0.53 0.74 0.91 v v ih input high voltage (single-ended) 1.275 1.56 1.275 1.56 1.275 1.56 v v il input low voltage (single-ended) 0.63 0.965 0.63 0.965 0.63 0.965 v v pp peak-to-peak input voltage 150 800 1200 150 800 1200 150 800 1200 v v cmr input high voltage common mode range; note 2 1.2 2.5 1.2 2.5 1.2 2.5 v i ih input high current pclk0, pclk1 npclk0, npclk1 200 200 200 a i il input low current pclk0, pclk1 -10 -10 -10 a npclk0, npclk1 -200 -200 -200 a
rev a 6/30/15 6 low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 853S111AI data sheet table 4d. ecl dc characteristics, v cc = 0v; v ee = -3.465v to -2.375v, t a = -40c to 85c note: input and output par ameters vary 1:1 with v cc . v ee can vary +0.925v to -0.5v. note 1: outputs terminated with 50 ? to v cco ? 2v. note 2: single-ended input operation is limited. v cc ? 3v in lvpecl mode. note 3: common mode voltage is defined as v ih . ac electrical characteristics table 5. ac characteristics, v cc = v cco = -3.465v to -2.375v or v cc = v cco = 2.375v to 3.465v; v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed ov er the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow great er than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters are measured at f out ? 1ghz, unless otherwise noted. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltag e, and with equal load conditio ns. measured at the output dif ferential cross points. note 3: defined as skew between outputs on different devices oper ating at the same supply voltage, same temperature and with eq ual load conditions. using the same type of inputs on each devi ce, the outputs are measured at the differential cross points. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter -40c 25c 85c units min typ max min typ max min typ max v oh output high voltage; note 1 -1.030 -0.94 -0.85 -1.140 -0.97 -0.85 -1.24 -0.98 -0.85 v v ol output low voltage; note 1 -1.86 -1.7 2 -1.59 -1.89 -1.75 -1.59 -1.97 -1.76 -1.59 v v ih input high voltage (single-ended) -1.225 -0.94 -1.225 - 0.94 -1.225 -0.94 v v il input low voltage (single-ended) -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 v v bb output voltage reference; note 2 -1.44 -1.32 -1.44 -1.32 -1.44 -1.32 v v pp peak-to-peak input voltage 150 800 1200 150 800 1200 150 800 1200 v v cmr input high voltage common mode range; note 3 v ee +1.2 0 v ee +1.2 0 v ee +1.2 0 v i ih input high current pclk0, pclk1 npclk0, npclk1 200 200 200 a i il input low current pclk0, pclk1 -10 -10 -10 a npclk0, npclk1 -200 -200 -200 a symbol parameter -40c 25c 85c units min typ max min typ max min typ max f out output frequency 2.5 2.5 2.5 ghz t pd propagation delay; note 1 450 575 700 490 625 745 550 650 800 ps t sk(o) output skew; note 2, 4 30 55 30 55 30 55 ps t sk(pp) part-to-part skew; note 3, 4 100 250 100 250 100 250 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, 12khz - 20mhz 0.07 0.07 0.07 ps t r / t f output rise/fall time 20% to 80% 85 200 315 85 200 285 85 200 315 ps
low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 7 rev a 6/30/15 853S111AI data sheet additive phase jitter the spectral purity in a band at a sp ecific offset from the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamenta l frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specifie d, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is ma thematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lowe r. the phase noise is dependent on the input source and measurement equipment. the source generator "rhode & schwartz sma 100a signal generator 9khz ? 6ghz as external input to a hewlett packard 8133a 3ghz pulse generator". additive phase jitter @ 155.52mhz 12khz to 20mhz = 0.07ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
rev a 6/30/15 8 low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 853S111AI data sheet parameter measureme nt information lvpecl output load ac test circuit part-to-part skew output rise/fall time differential input level output skew propagation delay scope qx nqx v ee v cc, 2v -1.465v to -0.375v v cco t sk(pp) part 1 part 2 nqx qx nqy qy nq0:nq9 q0:q9 v cc v ee v cmr cross points v pp npclk pclkx nqx qx nqy qy t pd nq0:nq9 q0:q9 npclkx pclkx
low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 9 rev a 6/30/15 853S111AI data sheet application information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
rev a 6/30/15 10 low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 853S111AI data sheet lvpecl clock input interface the pclk /npclk accepts lvpec l, lvds, sstl, cml and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of t he driver component to confirm the driver termination requirements. figure 2a. pclk/npclk input driven by a 3.3v lvpecl driver figure 2c. pclk/npclk input driven by an sstl driver figure 2e. pclk/npclk input driven by a cml driver figure 2b. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple figure 2d. pclk/npclk input driven by a 3.3v lvds driver figure 2f. pclk/npclk input driven by a built-in pullup cml driver r3125 r4125 r184 r284 3.3v zo = 50 zo = 50 pclknpclk 3.3v 3.3v lvpecl lvpecl input p c l k np c l k lvpecl in p u t ss t l 2. 5v 2. 5v 3 . 3v pclknpclk lvpecl input cml 3.3v zo = 50 zo = 50 3.3v 3.3v r150 r250 r150 r250 r5100 - 200 r6100 - 200 pclkvbb npclk 3.3v lvpecl 3.3v zo = 50 zo = 50 3.3v lvpecl input c1c2 pclknpclk vbb 3.3v lvpecl input r11k r21k 3.3v zo = 50 zo = 50 c1c2 r5100 lvds c30.1f pclknpclk 3.3v lvpecl input 3.3v zo = 50 zo = 50 r1100 cml built-in pullup
low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 11 rev a 6/30/15 853S111AI data sheet recommendations for unused output pins inputs: pclk/npclk inputs for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. for applications outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both si des of the differential output pair should either be left floating or terminated. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current pa th to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl output termination figure 3b. 3.3v lvpecl output termination r184 ? r284 ? 3.3v r3125 ? r4125 ? z o = 50 ? z o = 50 ? input 3.3v 3.3v +_
rev a 6/30/15 12 low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 853S111AI data sheet termination for 2.5v lvpecl outputs figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c. figure 4a. 2.5v lvpecl driver termination example figure 4c. 2.5v lvpecl driver termination example figure 4b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1250 r3250 r262.5 r462.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 r318 + ?
low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 13 rev a 6/30/15 853S111AI data sheet schematic example this application note provides a general design guide using 853S111AI lvpecl buffer. figure 5 shows a schematic example of the 853S111AI lvpecl clock buffer. in this example, the input is driven by an lvpecl driver. clk_sel is set at logic high to select pclk0/npclk0 input. figure 5. 853S111AI example lvpecl clock output buffer schematic c4 0.1uf c6 (option) 0.1u zo = 50 r750 zo = 50 r250 vcc r150 vcc vcc=3.3v c7 (option) 0.1u r350 (u1-16) u1 ics853111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 vcc clk_sel pclk0 npclk0 vbb pclk1 npclk1 vee vcco nq9 q9 nq8 q8 nq7 q7 vcco nq6 q6 nq5 q5 nq4 q4 nq3 q3 vcco q0 nq0 q1 nq1 q2 nq2 vcco r41k zo = 50 c2 0.1uf (u1-9) r850 zo = 50 ohm c8 (option) 0.1u +- c5 0.1uf r10 50 r11 50 3.3v lvpecl +- vcc (u1-32) r13 50 c1 0.1uf zo = 50 ohm r9 50 c3 0.1uf (u1-25) vcc zo = 50 (u1-1)
rev a 6/30/15 14 low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 853S111AI data sheet power considerations this section provides information on power dissipa tion and junction temperature for the 853S111AI. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 853S111AI is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 74ma = 256.41mw ? power (outputs) max = 32.59mw/loaded output pair if all outputs are loaded, the total power is 10 * 32.59mw = 325.90mw total power_ max (3.8v, with all outputs switching) = 256.41mw + 325.90mw = 582.31mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bon d pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming a moderate air flow of 2.5 meter per second and a multi-layer board, the appropriate value is 67.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.582w * 67.7c/w = 124.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 32 lead lqfp, forced convection ? ja by velocity meters per second 012 . 5 multi-layer pcb, jedec standard test boards 80.9c/w 71.4c/w 67.7c/w
low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 15 rev a 6/30/15 853S111AI data sheet 3. calculations and equations. the purpose of this section is to calculate the power dissipation for the lvpecl output pair. lvpecl output driver circuit a nd termination are shown in figure 6. figure 6. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.85v (v cco_max ? v oh_max ) = 0.85v ? for logic low, v out = v ol_max = v cco_max ? 1.59v (v cco_max ? v ol_max ) = 1.59v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? ( vcco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.85v)/50 ? ] * 0.85v = 19.55mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l ] * (v cco_max ? v ol_max ) = [(2v ? 1.59v)/50 ? ] * 1.59v = 13.04mw total power dissipation per output pair = pd_h + pd_l = 32.59mw v out v cco v cco - 2v q1 rl 50
rev a 6/30/15 16 low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 853S111AI data sheet reliability information table 7. ? ja vs. air flow table for a 32 lead lqfp transistor count the transistor count for 853S111AI is: 365 this device is pin and functional compatible with and is the suggested replacement for the ics853111a. ? ja vs. air flow meters per second 012 . 5 multi-layer pcb, jedec standard test boards 80.9c/w 71.4c/w 67.7c/w
low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 17 rev a 6/30/15 853S111AI data sheet package outline and package dimensions package outline - g suffix for 32 lead lqfp table 8. package dimensions for 32 lead lqfp reference document: jedec publication 95, ms-026 -hd version eposed pad down jedec variation: bba all dimensions in millimeters symbol minimum nominal maximum n 32 a 1.60 a1 0.05 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.60 ref. e 0.80 basic l 0.45 0.60 0.75 ? 0 7 ccc 0.10
rev a 6/30/15 18 low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 853S111AI data sheet ordering information table 9. ordering information note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configur ation and are rohs compliant. table 10. pin 1 orientation in tape and reel packaging part/order number marking package shipping packaging temperature 853s111ayilf ics53s111ail 32 lead lqfp tray -40 ? c to 85 ? c 853s111ayilft ics53s111ail 32 lead lqfp tape & reel, pin 1 orientation: eia-481-c -40 ? c to 85 ? c 853s111ayilf/w ics53s111ail 32 lead lqfp tape & reel, pin 1 orientation eia-481-d -40 ? c to 85 ? c part number suffix pin 1 orientation illustration t quadrant 1 (eia-481-c) /w quadrant 2 (eia-481-d)
low skew, 1-to-10, differential-to-lvpecl/ecl fanout buffer 19 rev a 6/30/15 853S111AI data sheet revision history sheet rev table page description of change date a t10 t9 1818 added pin 1 orientation in tape and reel table. ordering information - added w part number. 6/30/15
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to mo dify the products and/or specifications described herein at any time and at idt?s sole discretion. all informatio n in this document, including descriptions of product features and performance, is subject to change without notice. p erformance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in custom er products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of othe rs. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at th eir o wn risk, absent an express, written agreement by idt. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licen ses are implied. this produ ct is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary envi ronmental requirements are not recomme nded without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any id t product for use in life support devices o r critical medical instruments. integrated device technology, idt and the idt logo are registered trademarks of idt. product specifica tion subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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